The present invention relates to a semiconductor device formed on an insulator substrate or on an SOI (silicon on insulator) substrate in which a single crystalline silicon thin film is formed on an insulator film, and also related to a method for fabricating the semiconductor device.
In recent years, in the field of portable communication units such as cellular phone units, a device operating with low voltage, high speed, and low consumption power has been demanded. In order to satisfy these requirements or realize these properties, various attempts have been vigorously carried on by forming a transistor on an insulator substrate or on an SOI substrate, in which a semiconductor film is formed on an insulator film (hereinafter, simply referred to as an SOI transistor), and thereby reducing the parasitic capacitance or the like.
The structure of the conventional SOI transistor will be described with reference to the drawings.
FIG. 11 is a cross-sectional view of the conventional SOI transistor.
As shown in FIG. 11, an insulator layer 702 of an oxide film is formed on a p-type single crystalline silicon substrate 701. A silicon layer 703 used as the active region of the transistor is formed on the insulator layer 702. A LOCOS film 704 is formed for the purpose of isolating respective regions of the silicon layer 703 from each other just like islands. A gate oxide film 705 is selectively formed on each of the isolated regions of the silicon layer 703, and a gate electrode 707 of a polysilicon film is formed on the gate oxide film 705. Sidewalls 708 are formed on the sides of the gate electrode 707. A channel region 714 is formed in the silicon layer 703 just under the gate oxide film 705 and sandwiched by a source region 709 and a drain region 710, which contain a high-concentration impurity. An interlevel insulator film 711 of a BPSG film or the like, contact holes 712, and a metal interconnection layer 713 as an electrode are formed on the LOCOS film 704, the gate electrode 705, the source region 709 and the drain region 710.
FIGS. 12a to 12e are cross-sectional views depicting the fabricating process of the conventional SOI transistor.
SOI substrates can be classified into SIMOX substrates, bonded substrates, and other types of substrates. The SOI substrate to be described herein has a three-layer structure: a silicon substrate 701; an insulator layer 702 of a silicon oxide film 701 formed thereon; and a silicon layer 703 formed further thereon as the uppermost layer.
First, as shown in FIG. 12a, the LOCOS film 704 is formed by selective oxidation technique by using a mask consisting of a pad oxide film 721 and a silicon nitride film 722, thereby isolating the respective regions of the silicon layer 703 from each other just like islands.
Then, as shown in FIG. 12b, after removing the pad oxide film 721 and the nitride film 722, a p-type impurity is implanted in order to control the threshold value.
Next, as shown in FIG. 12c, after forming a silicon oxide film and a polysilicon film in this order on the silicon layer 703, the gate oxide film 705 and the gate electrode 707 are formed by patterning, and then the sidewalls 708 are formed on the sides of the gate electrode 707.
Subsequently, as shown in FIG. 12d, n-type impurity ions are implanted into the silicon layer 703 by using the gate electrode 707 as mask, thereby forming the source region 709 and the drain region 710 in a self-aligned manner.
Finally, as shown in FIG. 12e, after the interlevel insulator film 711 is deposited, the contact holes 712 are formed in the interlevel insulator film 711. After the metal interconnection layer 713 is deposited to fill up the contact holes 712 and to extend over the interlevel insulator film 711, the layer 713 is patterned.
By performing these process steps, the SOI transistor shown in FIG. 11 is completed.
However, such an n-channel-type SOI transistor where the silicon layer formed on the SOI substrate is isolated by the LOCOS film and the potential of the channel region is electrically floating, has the following two problems.
Firstly, in an MOS transistor, if the drain voltage is high enough, the electrons implanted into the channel region from the source region have so high energy in a region near the drain that that they cause impact ionization and generate hole-electron pairs. In a normal bulk transistor, generated electrons move to the drain region while the holes move to the inside of the substrate, causing not so serious problem. However, in the SOI transistor where the channel region 714 is electrically floating, holes are accumulated in a region of the electrically floating channel region 714 in the vicinity of the source region 709. Then, the accumulated holes lower the energy barrier between the source region and the channel region, causing a bipolar operation due to the amplification action similar to that of a bipolar transistor and increasing the current flowing in the channel region. This causes a problem that the source-drain breakdown voltage decreases.
Secondly, the use of a LOCOS film for the isolation of transistors generally causes a bird""s beak in the isolated area. Thus, in the process step shown in FIG. 12b, the impurity concentration implanted into the portion of the silicon layer 703 under the bird""s beak becomes lower than that of the other channel region 714. As a result, a parasitic transistor, i.e., a so-called an edge transistor, where the portion under the bird""s beak becomes a channel region, is formed.
FIGS. 13a and 13b are respectively a plan view and a cross-sectional view taken along the line XIIIxe2x80x94XIII for illustrating edge transistors formed on both ends of a main transistor, which is an original SOI transistor. As shown in FIG. 13a, in addition to the current (see the bold arrow in FIG. 13a) flowing through the main transistor, current also flows through the edge transistors generated on both ends (see the fine arrows in FIG. 13a). In an SOI transistor having no well structure, since the impurity concentration in the silicon layer just under the bird""s beak is lower than that of the channel region, the threshold value of the edge transistors becomes lower than that of the main transistor. Consequently, as shown in FIG. 14, if the voltage to be applied to the gate electrode is being increased, the edge transistors are turned ON before the main transistor is turned ON. As a result, the sub threshold property has a hump, causing a problem that the leakage current during the stand-by mode of the transistor increases.
An object of the present invention is to improve the reliability of an SOI transistor, formed to be isolated by a LOCOS film on a region on an SOI substrate and having a channel region with an electrically floating potential, by increasing source/drain breakdown voltage and by preventing leakage current from increasing during the stand-by thereof.
In order to accomplish this object, the present invention provides a region for eliminating carriers in the vicinity of the channel region of the SOI transistor such as a lattice defect region containing a lot of lattice defects functioning as the center of recombination, and/or a high-concentration diffusion region constituting a diode between the source/drain regions.
The semiconductor device of the invention includes: a substrate having an insulator layer thereon; a semiconductor layer of a first conductivity type formed on the insulator layer, part of the semiconductor layer functioning as a channel region; a gate insulator film formed on the channel region of the semiconductor layer; a gate electrode formed on the gate insulator film; source/drain regions of a second conductivity type formed in the semiconductor layer so as to sandwich the channel region therebetween; and a hole-eliminating region having a function of preventing the accumulation of holes of hole-electron pairs generated in the channel region, the hole-eliminating region being formed in a region of the semiconductor layer and adjacent to one of the source/drain regions and to the channel region.
In such a structure, when hole-electron pairs are generated in the channel region during the operation of the semiconductor device, the holes gather in parts of the channel region in the vicinity of the source/drain regions or in the source/drain regions. However, the holes are soon eliminated because the hole-eliminating region is provided to be adjacent to the channel region and either the source region or the drain region. Consequently, no bipolar operation results from the accumulation of holes, thereby maintaining the source/drain breakdown voltage at a high level.
In the semiconductor device, the hole-eliminating region may include two separate regions in the semiconductor layer, one of the two regions being adjacent to the source and channel regions, while the other region of the two being adjacent to the drain and channel regions.
In such a structure, in both regions neighboring the source/drain regions, holes are eliminated as a result of recombination. Thus, no bipolar operation results from the accumulation of holes, no matter how the level relationship varies between the voltages applied to the source/drain regions of the semiconductor device.
The semiconductor device may further include an on-gate silicide film formed on the gate electrode and on-substrate silicide films formed on the source/drain regions, respectively, each of the on-substrate silicide films being spaced from the gate electrode via a gap. The hole-eliminating regions may be located below the respective gaps between the on-substrate silicide films and the gate electrode.
As a result, a semiconductor device having reduced gate and/or contact resistance can be obtained, in addition to the above-mentioned effects.
In the semiconductor device, the hole-eliminating region may be a lattice defect region formed by introducing a latice defect to be a center of recombination.
In such a structure, even if the holes of hole-electron pairs generated in the channel region gather in the regions of the channel region neighboring the source/drain regions or in the source/drain regions, the holes are recombined with electrons and soon eliminated in a lattice defect region containing a lot of lattice defects to be the center of recombination.
In the semiconductor device including the lattice defect region, the lower part of the channel region is preferably a high-concentration channel region containing an impurity of the second conductivity type having a concentration higher than a concentration in the channel region.
In such a structure, the threshold voltage of a parasitic transistor, operating in the semiconductor device separately from the original transistor by using a region of the semiconductor layer neighboring the boundary between the element isolation and the semiconductor layer as a channel region, is increased. Therefore, as represented by the sub-threshold characteristics thereof, the original semiconductor device is first turned ON and then the parasitic transistor is turned ON. In particular, if the element isolation is formed of a LOCOS film, the threshold voltage of the parasitic transistor is increased because of the presence of a high-concentration channel region even in a part of the semiconductor layer below the bird""s beak of the LOCOS film. That is to say, since the operation of the parasitic transistor is restricted when a low voltage is applied to the gate, a hump can be eliminated from the sub-threshold characteristics and OFF leakage current is reduced.
The lattice defect region may be formed to entirely cover lower parts of the source, drain and channel regions in the semiconductor layer.
In such a structure, since a region for eliminating holes becomes larger, the holes of the hole-electron pairs are eliminated sooner. Furthermore, the fabricating process can be simplified because the atoms generating lattice defects may be introduced into the entire surface of the substrate.
The same impurity may be introduced into the lattice defect region and the high-concentration channel region.
In such a structure, both lattice defect region and high-concentration channel region can be simultaneously formed by introducing impurity only once if the peak of the impurity concentration is controlled by utilizing the fact that the lattice defects are generated when the impurity concentration reaches a certain level. As a result, the fabrication process can be simplified and the fabrication costs can be reduced.
If the semiconductor device is an n-channel type transistor, atoms of a Group 3b element having a larger atomic radius than an atomic radius of an element composing the semiconductor layer may be introduced into the lattice defect region.
Consequently, the number of lattice defects in the lattice defect region increases, which enhances the function of eliminating the holes.
If the semiconductor layer is composed of silicon single crystals, the Group 3b element is preferably at least one of gallium, indium and thallium.
Atoms of a Group 4b element may be introduced into the lattice defect region.
In such a case, the electrical properties of the semiconductor layer are not adversely affected by the atoms introduced into the lattice defect region.
The Group 4b element is preferably at least one of carbon, silicon and germanium.
The atoms of a Group 0 element (inert gas) may be introduced into the lattice defect region.
In such a case, the electrical properties of the semiconductor layer are not adversely affected by the atoms introduced into the lattice defect region.
The Group 0 element is preferably at least one of argon, krypton and xenon.
In the semiconductor device, the hole-eliminating region may be a high-concentration diffusion layer containing an impurity of a second conductivity type having a concentration higher than a concentration in the channel region.
Consequently, PN diodes are constituted by the high-concentration diffusion layer and the source/drain regions. Thus, even if the holes of hole-electron pairs generated in the channel region gather in the parts of the channel region neighboring the source/drain regions or in the source/drain regions, the holes flow to the source/drain regions and are eliminated soon.
1019 to 1021 impurity atoms/cm3 of the second conductivity type are preferably introduced into the high-concentration diffusion region.
The first method for fabricating a semiconductor device according to the present invention includes the steps of: (a) forming an element isolation film on an SOI substrate including at least an insulator layer and a semiconductor layer formed on the insulator layer, the element isolation film surrounding the semiconductor layer; (b) forming a lattice defect region, a high-concentration channel region and a channel region in the semiconductor layer by implanting, into the semiconductor layer, impurity ions of a first conductivity type, having an atomic radius larger than an atomic radius of an element composing the semiconductor layer, such that a concentration of the semiconductor layer reaches a maximum in a region in the vicinity of an interface between the semiconductor layer and the insulator layer; (c) forming a gate insulator film on the semiconductor layer; (d) forming a gate electrode on the gate insulator film; (e) forming source/region regions in respective regions of the semiconductor layer by introducing an impurity of a second conductivity type into the semiconductor layer by using the gate electrode as a mask, the source/drain regions being located on right and left sides of the gate electrode; and (f) diffusing and activating the impurity of the first conductivity type and the impurity of the second conductivity type by heat treatment.
According to this method, the lattice defect region can be formed to entirely cover the lower part of the semiconductor layer, and the high-concentration channel region and the channel region can be formed thereon by implanting impurity ions having a larger atomic radius than that of the element composing the semiconductor layer only once. Thus, a semiconductor device attaining the above-mentioned effects can be obtained by performing an extremely small number of process steps.
In the first method for fabricating a semiconductor device, if the semiconductor device is an n-channel type transistor, then ions of a Group 3b element may be used as the impurity ions of the first conductivity type in the step (b).
According to this method, a p-type channel region and the high-concentration channel region can be formed simultaneously with the lattice defect region. Thus, an SOI transistor having an excellent source/drain breakdown voltage can be obtained for an n-channel-type MOS transistor causing a problem of bipolar operation.
If the semiconductor layer is composed of silicon single crystals, then ions of at least one of gallium, indium and thallium are used as the ions of the Group 3b element in the step (b).
Since any of these elements has an atomic radius larger than that of silicon widely used for semiconductor layer, a larger number of lattice defects can be generated by introducing a smaller amount of impurity.
The second method for fabricating a semiconductor device according to the present invention includes: (a) forming an element isolation film on an SOI substrate including at least an insulator layer and a semiconductor layer formed on the insulator layer, the element isolation film surrounding the semiconductor layer; (b) implanting, into the semiconductor layer, ions of an element having such properties as causing lattice defects in the semiconductor layer, such that a concentration of the semiconductor layer reaches a maximum in a region in the vicinity of an interface between the semiconductor layer and the insulator layer; (c) forming a high-concentration channel region and a channel region by implanting impurity ions of a first conductivity type into the semiconductor layer such that the concentration of the semiconductor layer reaches a maximum in a bottom region of the semiconductor layer; (d) forming a gate insulator film on the semiconductor layer; (e) forming a gate electrode on the gate insulator film; (f) forming source/region regions in respective regions of the semiconductor layer by introducing an impurity of a second conductivity type into the semiconductor layer by using the gate electrode as a mask, the source/drain regions being located on right and left sides of the gate electrode; and (g) diffusing and activating the impurity of the first conductivity type and the impurity of the second conductivity type by heat treatment.
This method requires additional process steps as compared with the first method for fabricating a semiconductor device. However, a semiconductor device attaining the above-described effects can be obtained with more certainty.
In the second method for fabricating a semiconductor device, the types of atoms to be introduced for forming a lattice defect region may be selected as will be described below in the same manner as in the invention relating to the semiconductor device.
In the second method for fabricating a semiconductor device, in the step (b), ions of a Group 4b element may be used as the ions of the element having such properties as causing the lattice defects.
In the step (b), ions of at least one of carbon, silicon and germanium may be used as the ions of the Group 4b element.
In the second method for fabricating a semiconductor device, in the step (b), ions of a Group 0 element may be used as the ions of the element having such properties as causing the lattice defects.
In the step (b), ions of at least one of argon, krypton and xenon are preferably used as the ions of the Group 0 element.
The third method for fabricating a semiconductor device according to the present invention includes the steps of: (a) forming an element isolation film on an SOI substrate including at least an insulator layer and a semiconductor layer formed on the insulator layer, the element isolation film surrounding the semiconductor layer; (b) forming a semiconductor layer of a first conductivity type including at least a channel region in the semiconductor layer by introducing an impurity of the first conductivity type into the semiconductor layer; (c) forming a gate insulator film on the semiconductor layer; (d) forming a gate electrode on the gate insulator film; (e) forming insulator sidewalls on both side faces of the gate electrode; (f) forming source/drain regions in respective regions of the semiconductor layer by introducing an impurity of a second conductivity type into the semiconductor layer by using the gate electrode and the insulator sidewalls as a mask, the source/drain regions being located on right and left sides of the gate electrode; (g) forming silicide films on the gate electrode and the source/drain regions, respectively; (h) selectively removing the insulator sidewalls; (i) implanting ions of a hole-eliminating element into the semiconductor layer by using the silicide films as a mask such that a concentration of the semiconductor layer reaches a maximum in a region in the vicinity of an interface between the insulator layer and the semiconductor layer; and (j) diffusing and activating the impurity of the first conductivity type and the impurity of the second conductivity type by heat treatment.
According to this method, a hole-eliminating element can be introduced only into limited parts of the channel region in the vicinity of the ends thereof. Thus, it is possible to prevent with certainty the hole-eliminating element from adversely affecting the characteristics of the source/drain regions (such as an increase in source/drain resistance, junction leakage or junction capacitance).
In such a case, in the step (i), ions of an element having such properties as causing lattice defects may be used as the ions of the hole-eliminating element.
Moreover, in the step (b), the impurity ions of the first conductivity type are preferably implanted into the semiconductor layer such that a concentration of the semiconductor layer reaches a maximum in a bottom region of the semiconductor layer, thereby forming a high-concentration channel region and the channel region in the semiconductor layer.
In the third method for fabricating a semiconductor device, in the step (i), impurity ions of the first conductivity type having a concentration higher than a concentration in the channel region may be used as the ions of the hole-eliminating element.
In such a case, the dose of the impurity ions of the first conductivity type is preferably set at 5xc3x971013/cm2 or larger.